The present invention relates to a current source circuit which is used for a digital-to-analog converter (to be referred to as a D/A converter hereinafter) and which produces a plurality of weighted current outputs.
As a current source circuit for producing a plurality of weighted current outputs, a current source circuit as shown in FIG. 1 is conventionally known. Referring to FIG. 1, npn transistors Q01, Q11, Q21 and Q31 are output transistors at the collectors of which are obtained weighted current outputs. NPN transistors Q02, Q12, Q22 and Q32 are shunting transistors through the collector-emitter paths of which flow currents which are equal to the currents flowing to the transistors Q01, Q11, Q21 and Q31. Reference symbol CS01 denotes a current source of a current I. Voltage inputs V1, V2, V3 and V4 are respectively supplied to current division stages each consisting of the transistors Q01 and Q02, the transistors Q11 and Q12, the transistors Q21 and Q22, and the transistors Q31 and Q32. Reference symbol "+" denotes the voltage potential of a first power source (not shown), while reference symbol "-" denotes the voltage potential of a second power source (not shown) which is lower than that of the first voltage source.
In the current source circuit as shown in FIG. 1, currents I1, I2, I3 and I4 which are respectively 1/2, 1/4, 1/8 and 1/16 the current I flowing to the current source CS01 are obtained at the collectors of the output transistors Q01, Q11, Q21 and Q31. Since the current source circuit as shown in FIG. 1 is of the four-output configuration, it may be used as the current source for a D/A converter of 4-bit type. Due to its simple configuration, the current source circuit of this type makes the configuration of the D/A converter simpler as well.
However, with this current source circuit, when the currents flow to the collectors of the output transistors Q01 to Q31 (collectively referring to the transistors Q01, Q11, Q21 and Q31) and the shunting transistors Q02 to Q32 (collectively referring to the transistors Q02, Q12, Q22 and Q32), the output currents from the emitters thereof will include errors corresponding to the respective base currents. Thus, the currents I1, I2, I3 and I4 flowing to the respective transistor stages or the current division stages do not become exactly 1/2, 1/4, 1/8 and 1/16 the current I. For this reason, with a D/A converter incorporating such a current source circuit, D/A conversion may not be expected to be at high accuracy.
The errors of the currents I1, I2, I3 and I4 will now be described.
Let .alpha. denote the common base current amplification factor of each of the transistors Q01 to Q31 and the transistors Q02 to Q32, and the output currents I1, I2, I3 and I4 are then given by the following relations: EQU I1=.alpha./2I (1) EQU I2=.alpha..sup.2 /4I (2) EQU I3=.alpha..sup.3 /8I (3) EQU I4=.alpha..sup.4 /16I (4)
The errors included in the output currents I1, I2, I3 and I4 will be obtained from the relations (1), (2), (3) and (4). Let .beta. denote the common emitter current amplification factor of each of the transistors Q01 to Q31 and the transistors Q02 to Q32, and then we obtain: EQU .alpha.=.beta./(.beta.+1) (5)
Substitution of relation (5) in each of relations (1) to (4) provides: ##EQU1##
If .beta.=100, the errors of the currents I1 to I4 are obtained as follows:
Error of the output current I1: -1% PA1 Error of the output current I2: -2% PA1 Error of the output current I3: -3% PA1 Error of the output current I4: -4%
From these errors of the output currents obtained in this manner, it is seen that the errors increase as the number of current division stages increases, i.e., as the number of output currents increases. It follows from this that, with a D/A converter incorporating such a current source circuit, the accuracy of D/A conversion will be degraded as the number of bits of input data increases.